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Hi,
Some users have been sending init logs for Athlon kernels that
include PCI warning messages about the PCI cache line size
getting set incorrectly ... where the kernel thinks that the
right value is 16 bytes. Since 64 bytes is the right number,
it's dangerous to enable MWI on such systems.
This patch stops trying to use MWI; it's a workaround for the
misbehavior of that PCI cacheline-setting code. Please apply
to 2.5 and 2.4 trees.
- Dave
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--- 1.45/drivers/usb/host/ehci-hcd.c Mon Feb 24 03:30:38 2003
+++ edited/drivers/usb/host/ehci-hcd.c Wed Mar 19 07:05:33 2003
@@ -432,7 +432,11 @@
}
/* help hc dma work well with cachelines */
- pci_set_mwi (ehci->hcd.pdev);
+ /* NOTE: disabled until it works reliably ... some x86/Athlon
+ * kernels are thinking 16 byte cachelines, not 64 byte ones,
+ * so clearly the MWI prep logic is wrong.
+ */
+ // pci_set_mwi (ehci->hcd.pdev);
/* clear interrupt enables, set irq latency */
temp = readl (&ehci->regs->command) & 0xff;
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