Re: [patch 2.5] PCI MWI cacheline size fix

[Dave Jones]

On Thu, Mar 20, 2003 at 03:29:56PM +0300, Ivan Kokshaysky wrote:
 > On Thu, Mar 20, 2003 at 11:55:20AM +0000, Dave Jones wrote:
 > >  > +	else if (c->x86 > 6)
 > >  > +		pci_cache_line_size = 128 >> 2;	/* P4 */
 > >  >  
 > > 
 > > I'd feel more comfortable with this with a c->x86_vendor == X86_VENDOR_INTEL
 > > on the else if clause. The above code will silently break if for eg,
 > > VIA, Transmeta or any other clone manufacturer make a model 7 or higher CPU.
 > 
 > No, we'd just assume 128 bytes cache line size on such CPU, which is
 > safe unless it has cache lines larger than 128. But if we assume 32 bytes
 > while this new CPU has 64, MWI might corrupt memory by transferring
 > incomplete cache lines.

Ok, thanks for explaining this to me. Another possibility at future
proofing would be to actually run the cpuid function to get the
cacheline size, although as thats vendor (and in some cases model)
specific, it's probably more pain than its worth, so your method is
the safest way forward.

		Dave