> Yes, you're correct. It was SSE1, not SSE2.
> 
> The problem Zwane encountered is that early Athlons don't support SSE1,
> only XP+ do
hmm wouldn't they illegal op? Some tested this on an Athlon 600.
> To use it he would need an a new CONFIG split for Athlon XP and earlier
> Athlon. iirc it didn't make much difference on the athlon anyways which
> has quite fast locked operations on exclusive cachelines - sfence seems
> to be more useful on P4.
How about this instead then;
Index: linux-2.5.66/arch/i386/Kconfig
===================================================================
RCS file: /build/cvsroot/linux-2.5.66/arch/i386/Kconfig,v
retrieving revision 1.1.1.1
diff -u -p -B -r1.1.1.1 Kconfig
--- linux-2.5.66/arch/i386/Kconfig	24 Mar 2003 23:40:26 -0000	1.1.1.1
+++ linux-2.5.66/arch/i386/Kconfig	1 Apr 2003 16:02:46 -0000
@@ -368,6 +368,11 @@ config X86_PREFETCH
 	depends on MPENTIUMIII || MPENTIUM4 || MVIAC3_2
 	default y
 
+config X86_USE_SFENCE
+	bool
+	depends on MPENTIUM4
+	default y
+
 config X86_SSE2
 	bool
 	depends on MK8 || MPENTIUM4
Index: linux-2.5.66/include/asm-i386/system.h
===================================================================
RCS file: /build/cvsroot/linux-2.5.66/include/asm-i386/system.h,v
retrieving revision 1.1.1.1
diff -u -p -B -r1.1.1.1 system.h
--- linux-2.5.66/include/asm-i386/system.h	24 Mar 2003 23:40:20 -0000	1.1.1.1
+++ linux-2.5.66/include/asm-i386/system.h	1 Apr 2003 16:03:50 -0000
@@ -355,11 +355,15 @@ static inline unsigned long __cmpxchg(vo
 
 #define read_barrier_depends()	do { } while(0)
 
+#ifdef CONFIG_X86_USE_SFENCE
+#define wmb()	__asm__ __volatile__ ("sfence;": : :"memory")
+#else
 #ifdef CONFIG_X86_OOSTORE
 #define wmb() 	__asm__ __volatile__ ("lock; addl $0,0(%%esp)": : :"memory")
 #else
 #define wmb()	__asm__ __volatile__ ("": : :"memory")
 #endif
+#endif /* CONFIG_USE_SFENCE */
 
 #ifdef CONFIG_SMP
 #define smp_mb()	mb()
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