Wrong. On i486 and Pentium LOCK means bus lock. Period.
On P6 it is more complex than that. If the location you are locking is
cached in the processor performing the lock the processor may not assert
the LOCK on the bus. It will modify its internal view of it and let the
cache coherency mechanism handle the "problems".
> But i'll not bet on this until i read the manuals ;-))
yes, good idea. They are all on developer.intel.com, btw.
Regards,
Tigran.
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