Huh? LEA is just accessing what is, in effect, a third ALU. Either
should be the same speed, *but* you have to worry about scheduling,
which is CPU-dependent. P6 cores have two "normal" ALUs and one
address-generation one. One thing LEA lets you do is a three-register
operation, which the normal ALUs can't do:
lea eax,[ebx+esi]
... instead of ...
mov eax,ebx
add eax,esi
(On Crusoe, of course, either of these become a single VLIW "add" atom
and thus are completely equivalent.)
-hpa
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