>Maybe. We might lose an IRQ, we might take a wrong IRQ, we might also lose
>cache coherency missing a TLB flush. Most would probably be bad but Im not
>sure we'd take a hang from it.
If we miss a SMP tlb flush for a thread, a tlb entry could still point to
a physical page that is been added to the freelist. So a task on the other
cpu by could still write to such page while it's reused for some critical
kernel structure. However it's not a kind of thing easily reproducible and
it's not going to crash the machine so easily ;).
Andrea
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