Nordic Journal of Computing Bibliography

Carl Johan Lillieroth and Satnam Singh. Formal Verification of FPGA Cores. Nordic Journal of Computing, 6(3):299-319, Fall 1999.

A formal verification technique is presented which is suitable for the verification of standard components (cores) for programmable hardware (FPGAs). This technique can be viewed as a suitable complement to traditional techniques, such as simulation. We describe the modelling and verification of combinational and sequential components using the formal verification tool NP-Tools, and report successful verification of real cores.

Categories and Subject Descriptors: B.6.3 [Logic Design]: Design Aids; D.2.4 [Software Engineering]: Program Verification

Additional Key Words and Phrases: formal verification, cores, reconfigurable cores, core development methodology, intellectual property, FPGAs, equivalence checking, Stålmarck's Method

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