Errata File (February 2002)
             Computer Organization and Architecture, Fifth Edition
                               William Stallings
                      (Prentice-Hall, ISBN 0-13-081294-3)

------------------------------SYMBOLS USED-------------------------------
| ti = ith line from top;  bi = ith line from bottom; Fi = Figure i      |
| X -> Y = replace X with Y; Ti = Table i                                |
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PAGE    CORRECTION

161 b11: 100 and 200 -> 100 and 50

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//////////////////////////////// JANUARY LIST////////////////////////////
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 19 b17: 15,000 -> 1500

 58 F3.5: PC should be 301,302,303 in steps 2,4,6, because the PC is
          incremented at the end of the fetch cycle; narrative on 
          pp 58-59 should reflect this

 89 item e: all GNT lines -> all REQ lines

100 b6: access time or -> access time of

118 t3-4: cache and main memory -> cache and the processor

126 b2: 00A000 -> 008000     FF1000 -> FF8000
    F4.20: FFFF4, FFFF8, FFFFC -> FFFFF4, FFFFF8, FFFFFC

127 Title: Two-way -> k-way

128 F4.22: in cache, replace tag 001 with 02C, three times

144  Prob 4.14: L1,L2,L3,L4 -> L0,L1,L2,L3

167 t21: delete phrase "is larger than"

224 Prob 6.4: 6.4 -> 6.3

253 F7.17, Physical Address: Page Number -> Frame Number

280 T8.2: Biased rep. ranges from -7 to + 8 excluding -0

284 b1: exponent n should be n-1 both times

329 F9.3a: first line should be SUB Y, A, B

330 T9.1: T OP (T - 1) -> (T - 1) OP T

360 2 Address Instr: DIV (X <- X/Y)
    3 Address Instr: DIV (X <- Y/Z); 
                     for ADD, SUB, MUL, change second X to Y

361 Prob 9.8a: add * at end of line

376 F10.1e: arrow pointing to the register location should start from the
            "register field" of the instruction.

431 F11.17: Missing caption: (b) Branch history table strategy
            IPFAR = instruction prefetch address register

433 F11.18b: MOV Reg1,(Reg2) -> MOV Reg2,(Reg1)

452: F11.24a: lower left state should be "Predict Taken"

496 Pr 12.5,twice: S:=S-1 -> S:=S-K

535 b1: out-or-order -> out-of-order

635 t13: L3 caches are located in the BSNs

652 F16.12.c, 1st line: DO 50 J = 1, (N - 1)

665 line 6 of program: Load D(I),R3 /Memory (theta+I) <- (R3)/

670 b2: D = A OR (B' AND C)

683 FA.10b: X = BD' + BC' + B'CD
    TA.5, column C, index 5: 1 -> 0

685 Next to last equation: put two complement bars over entire last
                           expression.
    Last equation: should have each right side terms negated
                   and the whole right side negated

718 K: 210 -> 2^10
    M: 220 -> 2^20    2_220 -> 2,097,152

728 b3: SIGSCE Bulletin September 1996 -> SIGCSE Bulletin September 1990

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|       A current version of this file, named Errata-COA5e-mmyy,         |
|                  is available at WilliamStallings.com                  |
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