581365 Computer Organization II

Course exam 12.12.2007

1. LATCH, CONTROL, AND MICROINSTRUCTION [14p]

1. The picture below shows the structure of the S-R latch.

   

   1. How do you change the state of the S-R latch? Show that after a change the latch remains in the new state. (4 p)

   2. Where is a S-R latch used? Give a practical example. (1 p)

   3. What problems are there with the S-R latch ( for example compared with D flip-flop or J-K flip-flop)? (1 p)

2. How do hardwired control and microprogrammed control differ? What are their advantages and disadvantages? (4 p)

3. What is a microinstruction? How does horizontal microinstruction differ from vertical microinstruction? What are the advantages and disadvantages of both? (4 p)

2. CACHE AND TLB [16p]

1. Why are caches needed and why do they work? (2 p)

2. Why is a TLB used and why does it work? (2 p)

3. What are the similarities and differences of a cache and a TLB? How do the cache and the TLB relate to each other? (4p)

4. Assume that a system using (unrealistically) small cache memory refers to a 4-byte word using the byte address 0xA0B4 (i.e. the address is 16 bits long). Assume that the cache line size is 16 bytes and the cache size is 256 bytes. Draw a picture and explain how the solution finds the above mentioned byte from the cache, when the implementation is based on 2-way set associative mapping. Show clearly how the byte address is divided into separate fields used by the implementation. You may assume that the referenced data is found in the cache.( 8p)

3. PIPELINING [18 p]

1. How does the super-scalar processor functionality differ from a traditional pipelined processor? (2p)

2. What five factors limit the maximum performance of super-scalar processor pipeline? Give a concrete (machine language level) example on each factor. (10p)

3. The IA-64 architecture uses predication and control and load speculation. Explain what is meant by these. What is the aim for their usage? (6p)

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