[18 p] Dependencies. Assume that RISC architecture ALU instructions have
three register operands and that the result is stored into the first
(left-most) register. The architecture is implemented in ordinary (not
superscalar) pipelined fashion so that, in best case, one instruction can be
completed in each cycle. The pipeline has 5 phases (instruction fetch, instruction decode, register read, ALU, write back).
Observe the following set of instructions generated by the compiler (instruction number on left):
1 Load R2, VarX ; Regs(2) <- Mem(VarX)
2 Add R5, R5, R2 ; Regs(5) <- Regs(5) + Regs(2)
3 Loop Move R2, R6 ; Regs(2) <- Regs(6)
4 Add R3, R3, R2
5 Add R2, R3, R5
6 Jnzer R3, Loop
7 Move R1, R2
Many aspects in the given code segment may reduce the execution speed from the maximum possible.
- [6 p] Describe precisely the problem types data dependency, control dependency, and structural dependency. Mark in a clear way one occurrence of each problem type in the given code segment (if it appears there).
- [4 p] How can one avoid or reduce the performance effects caused by data, control or structural dependencies? Give one solution to each dependency type (two solutions for control dependency) and describe briefly how it works.
- [4 p] Assume now, that the architecture is implemented as superscalar with fetch policy fetch and decode 3 instructions at a time and issue policy out-of-order issue, out-of-order completion. Describe precisely new dependency types (output dependency, antidependency) and mark in a clear way one occurrence for each problem type in the given code segment (if it appears there).
- [4 p] How can one avoid or reduce the performance problems caused by these new dependency types given in part (c)? Give one solution to each new dependency type and describe briefly how it works.