581365-8 Computer Organization II (4 cu)
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Datororganisation II

Position in Curriculum

In new 1.8.2005 degree system the course is elective special course in Distributed Systems and Data Communication specialization area. In preceding degree system it was compulsory course in that specialization area. It is suitable also for other students who are interested in computer organization at hardware level.

The target audience for the course are the 2nd-4th year students.

Prerequisites

Course Computer Organization I, or the at least good knowledge on the topics in it.

Different Ways to Take This Course

One can take the course as

1. Lecture course (offered every Fall semester)
   • Lectures: 6 weeks, 4h/wk
   • Practice sessions: 6 weeks, 2h/wk
   • Course exam
2. Final exam

Please notice that the course exam for the lecture course can not be used as a final exam.
Lecture course homework points do not affect your grade in the final exam.

All exams can be taken in English, but you need to confirm this with the instructor one week before the exam.

Course Material and Exam

The course is based on textbook William Stallings, Computer Organization and Architecture, 6th Ed., Prentice Hall, 2003. The course covers Chapters 3, 4.1-3, 5.1-3, 8.3, and 9-15, as well as Appendix A.
(We assume that the Chapters 1-8 are mostly already known because of the prerequisites)

This is also the examination area for final exam.

Contents

• Machine language structure and features
• Logic circuits: AND, OR, ..., registers, ALU, memory
• Processor implementation: data path, control, memory, I/O
• Principles of pipelining, basic hazards and solution methods for them
• RISC, CISC, and superscalar architecture
• Memory hierarchy: caches, virtual memory and address translation logic
• I/O buses: ISA, PCI, USB, SCSI

Goals

We will cover lower level computer organization from circuit and logic level up to intruction set level, from the the user, compiler, or hardware architect viewpoint. The overall general goal is to understand how the hardware clock cycle will make the processor to execute instructions.

We will look at more detail instruction set structure and features, the operation of logic and memory circuits, the components of processor implementation, the problematics with processor pipelining, as well as the implementation of memory hierarchy and I/O.

The goals are better described in their own document.

Teemu Kerola