Department of Computer Science

Computer Organization II,  Autumn 2007, HW 6

These questions will be covered in practise session 5.12.2007

1. Problems 13.4 "Reorganize the code seguence in Figure 13.6d to reduce the number of NOOPs." and 13.8 [Sta06] ( 13.6 [Sta03]) " Add entries for the following processors to Table 13.7 (Table 13.8) a) Pentium II, b) PowerPC."

2. Problem 13.6 [Sta06] (13.5 [Stal03], 12.5 [Stal99])

3. Problem 13.7 [Sta06]:
   A RISC machine may do both a mapping of symbolic registers to actual registers and a rearrangement of instructions for pipeline efficiency. An interesting question arises a to the order in which these operations should be done. Consider the following program fragment:

               LD     SR1, A
               LD     SR2, B
               ADD    SR3, SR1, SR2
               LD     SR4, C
               LD     SR5, D
               ADD    SR6, SR4, SR5
   

   1. First do the register mapping and then any possible instruction reordering. How many machine registers are used? Has there been any pipeline improvement?
   2. Starting with the original program, now do the instruction reordering and then any possible mapping. How many machine registers are used? Has there been any pipeline improvement?

4. Problems 14.3 and 14.5 [Sta06] (14.3 and 14.5 [Sta03], 13.3 and 13.5 [Sta99]

5. [2 hwp] Problem 14.6 [Stal06]          (14.6 [Stal03], 13.6 [Stal99])
   Please note, that the comment fields given for instructions (I4) and (I6) are wrong.

6. [1 HWP] Please give course feedback.
   Give your comments to the following
   1. Study material (cource book, exercises, other)
   2. Some weak points in the course? Did it assume some information you didn't have from earlier studies?
   3. How to make the course still better? More about parallel processing (Chapter 18) instead of IA-64 (Chapter 15)? Some other changes in the content?
   These will be discussed in the practice session.
   Thanks!